1. Technical Field
The present disclosure relates to a sense-amplifier circuit for non-volatile memories that operates at low supply voltages; in particular, the following description will make specific reference, without this implying any loss of generality, to the use of this sense-amplifier circuit in a non-volatile EEPROM (Electrically Erasable and Programmable Read-Only Memory) of the type commonly used in a wide range of applications, amongst which automotive devices, telecommunications devices (for example, mobile phones, pagers), portable consumer devices (for example, smart cards, SIMs, video cameras and photographic cameras, portable computers) and data-processing devices in general (for example, personal computers).
2. Description of the Related Art
In a known way, a non-volatile memory made with semiconductor technology comprises a memory array constituted by a plurality of memory cells, arranged aligned in rows and columns and connected to appropriate selection and biasing elements and stages, which enable programming (or writing), erasing and reading thereof in respective operating conditions.
In particular, memory cells belonging to one and the same column have drain terminals connected (directly or selectively through respective selection switches) to one and the same bitline, i.e., a metal connection line that extends throughout the column and that enables biasing thereof at the desired voltages.
Programmed memory cells have a different threshold voltage from erased memory cells; the operation of reading (or verifying) of the contents of the memory cells thus envisages sensing of the current circulating in the same memory cells, in the presence of appropriate biasing conditions (which depend, among other things, upon the technology used).
For example, in the case of a non-volatile EEPROM, the memory cells are constituted by floating-gate transistors, and the erasing and programming operations envisage the injection and, respectively, the extraction of electrical charges into/from the floating-gate terminal of the floating-gate transistor via the tunnel effect (Fowler-Nordheim effect). An EEPROM cell has different threshold voltages according to whether it is in the programmed state or in the erased state (in particular it has a lower threshold voltage when programmed) so that, in the same biasing conditions, it supplies different reading currents according to its state (programmed or erased).
The reading (or verifying) operation is performed by means of a purposely provided sense-amplifier circuit, configured so as to compare the value of the current circulating in an appropriately biased memory cell with a reference current. In particular, the reference current can be the current circulating through a reference (or “virgin”) cell, made with the same technology as the memory cells, or, alternatively, be supplied by an appropriate current-generator circuit (for example, of the current-mirror type, operating on the basis of a suitably generated reference voltage, for example a band-gap voltage).
The sense-amplifier circuit is further configured so as to supply to the drain terminals of the memory cells subjected to reading (or verification of their contents) the biasing voltages, and thus so as to be able to drive, or precharge, the capacitive load constituted by the corresponding bitlines (which have in fact a capacitance proportional to their extension along the columns of the memory array).
In particular, the speed with which the sense-amplifier circuit is able to perform the current comparison (and hence switch high, or low, according to the relation between the current circulating in the memory cell and the reference cell) has a significant effect on the time for accessing the memory during reading.
In order to reduce the levels of consumption and the size of the electronic devices (for example, portable devices operating with a battery), there is the tendency to use low supply voltages and increasingly more scaled technologies (for example, CMOS technologies with a channel length of 90 nm).
In particular, problems arise in the integration of memory cells, for example EEPROM cells, in markedly scaled CMOS technologies, due to the need, for LV (low-voltage) transistors to operate at ever-lower voltages (for example, voltages lower than or equal to 1.35 or 1.2 V) so as to protect the gate oxides (which have thicknesses as low as approximately 20 Å).
The external supply voltages, on the other hand, albeit low in order to reduce consumption levels, are not scaled accordingly, necessitating the use of voltage converters (the so-called “voltage down converters”) for biasing the LV transistors in the memory.
If on the one hand these converters enable separation of the external supply from the one internal to the memory, on the other hand, at the peaks of current absorption by the internal circuitry, they are subject to inevitable drops, which may even be of the order of some hundreds of millivolts.
Consequently, if the converter tends to regulate the internal supply voltage to a value equal, for example, to 1.2 V (a typical operating voltage for 90-nm CMOS transistors), it is inevitable that, on account of the drops, the effective value of the voltage can even reach 1 V.
The foregoing involves considerable difficulties in the design of the memories, which on the one hand require high operating voltages in order to modify and read the contents of the memory cells, and on the other extremely low and stable supply voltages in order to bias the internal LV components.
In particular, design of the sense amplifiers is important in order to satisfy the following:                being able to drive capacitive loads, even of a high value;        being able to discriminate minimum differences of current (for example, in the order of 1 or 2 μA);        operating at low internal supply voltages (for example, lower than 1.35 V); and        performing reading in extremely short times (for example, in the region of 30 ns or less).        
Even though a wide range of sense-amplifier architectures is currently known, some of which are also able to operate at low supply voltages, none of them has proven altogether satisfactory as regards the aforesaid when the internal supply voltages drop to values of 1 V or less.
In particular, the document “A high performance very low voltage current sense-amplifier circuit for Non volatile Memories”, IEEE JSSC, vol. 40, No. 2, February 2005, discloses the architecture of a sense-amplifier circuit that is able to operate at internal supply voltages of as low as 1.35 V.
This circuit, which is depicted in FIG. 1, is generally based (see the aforesaid document for further details) on a differential architecture for the comparison between the current circulating in a memory cell (designated by Ic), through the corresponding bitline BL, and a reference current Iref. A voltage comparison is performed (by means of an amplifier stage formed by MOS transistors M15-M20) after an I/V (current/voltage) conversion starting from the aforesaid currents, and only after a precharging phase of the bitline capacitance has terminated (in such a way that voltage values are stabilized); an output signal Sout is thus generated.
In particular, a comparison stage (representing the core of the sense-amplifier circuit) is provided, made by a current mirror formed by NMOS comparison transistors M1, M2, which receive the currents to be compared Ic and Iref, and are appropriately biased by a current mirror formed by PMOS transistors M4-M6 (which in turn receives a current to be mirrored from an NMOS transistor M3 having on the gate terminal a pre-set voltage VREF, equal to a desired voltage for the bitline BL, with the memory cell not connected).
The circuit proves suited to operating at low voltages thanks to the presence of a precharging stage, constituted by PMOS transistors M12, M13 and by NMOS transistors M10, M11 in current-mirror configuration, which is able to supply a further supplement of current to the bitline BL selected during the phase of precharging of the line capacitance (in particular, the amount of supplementary current supplied to the bitline is modulated by the voltage present on the same bitline, via the NMOS transistor M14, which “turns off” the mirror when the bitline BL reaches a desired precharge level, when NMOS comparison transistors M1, M2 are turned on and the corresponding current mirror is enabled).
A slew-rate-increasing stage is moreover provided for increasing the switching speed of the sense-amplifier circuit, by increasing the biasing current with which the capacitive load of the bitline is precharged. This stage is constituted by NMOS transistors M7-M8, which, when biased by an appropriate current, increase by a mirroring factor (being coupled to NMOS transistor M3), the biasing current for the bitline BL during the precharging phase; NMOS transistor M9 causes this current increase action to be active only during the precharging phase, until the voltage on the bitline reaches a pre-set threshold value such as to turn on the comparison NMOS transistors M1, M2.
The circuit suffers, however, from a drawback that may limit its reading speed when very low voltages are used (for example, lower than 1.35 V), owing to the fact that the initial current peak may be insufficient when the current mirrors, on which the control and increase of the precharging current are based, start to suffer from the so-called “Early effect” (during the precharging phase, the current on the bitline is in fact supplied entirely by the same current mirrors).
Consequently, this circuit does not offer an adequate control of the bitline precharge for internal supply voltages in the region of, or lower than, 1 V, and moreover has access times that cannot be lower than approximately 30 ns for the same values of the internal supply voltage.